Recently, as MIS transistors which form semiconductor integrated circuits have been scaled, gate insulator thereof has become rapidly thinner. Consequently, influences of depletion in the gate electrode (polycrystalline silicon film) near the interfaces between the gate electrode and gate insulator caused when gate voltage is applied to a gate electrode to turn on a MIS transistor become more and more apparent. As a result, apparent thickness of the gate insulator becomes thicker, which makes it difficult to have sufficient ON current, and operation speed of the transistor is significantly reduced. Also, when the gate insulator becomes thinner, since a quantum effect called direct tunneling occurs, which makes electrons pass through the gate insulator, the leakage current is increased. For its solution, using materials having high permittivity for gate insulator is studied. For example, an insulating film having higher permittivity obtained by adding nitride to a silicon oxide film so that its nitride concentration becomes higher, and a high dielectric film which is so-called high-k film. As materials of the high-k film, hafnium oxide (HfO.sub.x) having a relative dielectric constant of about 20 to 25, materials having higher crystallization temperature obtained by combining this hafnium oxide with silicon (Si) or aluminum (Al) (HfAlO.sub.x, HfSiO.sub.x), and rare-earth oxides (such as La.sub.2O.sub.3, Y.sub.2O.sub.3) are promising.
When using such high dielectric constant film for the gate insulator, even the EOT (equivalent silicon oxide thickness) is the same, the actual physical thickness can be increased by a factor of “dielectric constant of a high dielectric constant film/dielectric constant of a silicon oxide film”. As a result, ensuring capacitance of the gate insulator, the leakage current can be reduced.
For example, in Japanese Patent Application Laid-Open Publication No. 7-030113 (Patent Document 1), a technique to obtain nitride of several atom percents near interface between gate insulator and semiconductor substrate except at the center portion in the channel direction under the gate insulator is disclosed.
Also, in Japanese Patent Application Laid-Open Publication No. 2002-26317, a technique to form a high-concentration nitride region at the interface between the substrate under the end portion of the gate electrode and gate insulator.
Also, in Japanese Patent Application Laid-Open Publication No. 2003-249649, a technique to introduce nitride near the both sides of the insulator.
Also, in OYO BUTSURI Vol. 72, Number 9 (2003), p. 1136-p. 1142 (Non-patent Document), a technique relates to a FinFET having a channel made to have a three-dimensional structure (Fin structure) to suppress short-channel effect.